1. Field of the Invention
The present invention relates to a fabrication method for a flash memory device. More particularly, the present invention relates to a fabrication method for a split-gate flash memory device.
2. Description of the Related Art
In general, the conventional structure of an erasable programmable read-only memory (EPROM) device is similar to that of the N-type metal-oxide-semiconductor (MOS), wherein the gate structure is the stacked gate type, comprising a polysilicon floating gate for charge storage and a control gate to control the storage and retrieval of information. Thus a typical EPROM unit comprises two gates, a floating gate and the underlying control gate. The control gate is connected to the word line, while the floating gate is maintained in a "floating" condition and has no connection with the external circuits. At present, the most popular type of flash memory device has been developed by Intel Corporation, in which the erasure operation can be conducted "block by block", and the erasure speed is fast. The erasure operation is completed in 1 to 2 seconds, greatly reducing the time and the cost of operation. The traditional stacked gate structure of the flash memory device, wherein the floating gate and the control gate are stacked on each other, often result in the problem of an over-erasure during the flash-memory device erasure operation.
To resolve the over-erasure problem in the traditional stacked gate structure of a flash memory device, a split gate flash memory device is being developed.
FIG. 1 is a schematic, cross-sectional view of a split-gate flash-memory device according to the prior art. The structure of the split-gate flash memory device includes a substrate 100, comprising a source region 102a and a drain region 102b. On the substrate 100 is a gate oxide layer 104, wherein a floating gate 106, a dielectric layer 108 and a control gate 110 are on the gate oxide layer 104.
The conventional flash memory device is formed by forming a source region 102a and a drain region 102b, respectively in the substrate 100. A dielectric layer (not shown) and a conductive layer (not shown) are formed on the substrate 100, immediately followed by a definition of the conductive layer and the dielectric layer to form a floating gate 106 and a gate oxide layer 104, respectively. The gate oxide layer 104 is formed on the substrate 100 at a side of the source region 102a or the drain region 102b, partially covering either the source region 102a or the drain region 102b.
The operation conditions of a conventional split-gate flash-memory device are summarized in Table 1.
TABLE 1 Operation Conditions of a Conventional Split-Gate Flash-Memory Device. Control Bit Line Operations Gate (Drain Region) Source Region Substrate Programming 8-12 V 3-8 V GND GND Erasure GND GND GND &gt;15V Reading Vcc 1-2 V GND GND
In a split gate flash memory device, the control gate 110 and the floating gate 106 are not completely stacked on each other, the problem of an excessive erasure as in the conventional stacked gate is thereby obviated. As the device dimensions are continuously being reduced, the distance between the source region 102a and the drain region 102b, however, also decreases. A short channel between the source region 102a and the drain region 102b is results, easily leading to the punch through effect. The dimensions of a split-gate flash-memory device, as a result, cannot be scaled-down.